S25FL128SDPNFI001

S25FL128SDPNFI001 is a flash memory. This family of device connects to a host system via a SPI. Traditional SPI single bit serial input and output (single I/O or SIO) is supported as well as optional two bit (dual I/O or DIO) and four bit (quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

• 128Mb density, 66MHz DDR speed
• Multi I/O command set and footprint compatible with S25FL-P SPI family
• Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR READ commands
• Quad-input page programming (QPP) for slow clock systems
• Automatic ECC-internal hardware error correction code generation with single bit error correction
• 100000 minimum program-erase cycling endurance
• 20 year data retention, minimum
• Status register bit to control protection against program or erase of a contiguous range of sectors
• Individual sector protection controlled by boot code or password
• 8-contact WSON package, industrial temperature rage from -40°C to +85°C