芯片, 时钟发生器, 710MHZ, QFN-24
- Supports single-ended or differential input clock signals
- Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) output
- Provides signal level translation
- Loss of signal (LOS) indicator allows system clock monitoring
- Output enable (OEB) pin allows glitchless control of output clocks
- 100ps Output-output skew
- 150fs RMS typical additive jitter
通信与网络, 光纤, 时钟与计时
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