FPGA配置内存, EEPROM, 1 Mbit, 33 MHz, 2线, DIP, 8 引脚
- In-System Programmable (ISP) via 2-wire bus
- Simple Interface to SRAM FPGAs
- Cascadable read-back to support additional configurations or higher-density arrays
- Very low-power CMOS EEPROM process
- Programmable reset polarity
- Emulation of the AT24CXXX serial EEPROMs
- Low-power standby mode
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