- Low-power advanced CMOS NOR flash process
- Endurance of 20000 program/erase cycles
- JTAG Command initiation of standard FPGA configuration
- Cascadable for storing longer or multiple bit streams
- Dedicated boundary-scan I/O power supply
- I/O Pins compatible with voltage levels ranging from 1.8 to 3.3V
CAD Models - Notice
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Use of these CAD models and other options provided are downloaded and used entirely at your own risk and by continuing you confirm acceptance of the above.
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