AD9250BCPZ-250

AD9250 is a dual, 14bit ADC with sampling speeds of up to 250MSPS designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. Typical applications include diversity radio systems, multimode digital receivers (3G) (TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE), DOCSIS 3.0 CMTS upstream receive paths, HFC digital reverse path receivers, I/Q demodulation systems, smart antenna systems, electronic test and measurement equipment, radar receivers COMSEC radio architectures, IED detection/jamming systems, general-purpose software radios and broadband data applications.

• 1.8V supply voltage
• Signal-to-noise ratio (SNR) = 70.6dBFS at 185MHz AIN and 250MSPS
• Spurious-free dynamic range (SFDR) = 88dBc at 185MHz AIN and 250MSPS
• Integer 1-to-8 input clock divider and IF sampling frequencies of up to 400MHz
• Internal analogue to digital converter (ADC) voltage reference
• Flexible analogue input range from 1.4Vp-p to 2Vp-p (1.75V p-p nominal)
• ADC clock duty cycle stabilizer, 95dB channel isolation/crosstalk and 1000MHz full power bandwidth
• Serial port control and energy saving power-down modes
• 48 lead LFCSP package
• Operating temperature range from -40°C to 85°C

Notes

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party