AD9689BBPZ-2600

AD9689 is a dual, 14bit, 2.6GSPS ADC. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analogue signals of up to 5GHz. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analogue input and clock signals are differential inputs. The ADC data outputs are internally connected to 4 DDCs through a crossbar mux. Typical applications include diversity multiband and multimode digital receivers, 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A, electronic test and measurement systems, phased array radar and electronic warfare, DOCSIS 3.0 CMTS upstream receive paths and HFC digital reverse path receivers.

• Noise density of -152dBFS/Hz at 2.56GSPS at full-scale voltage = 1.7V p-p
• SFDR at 2.56GSPS encode 73dBFS at 1.8GHz AIN at -2dBFS and full-scale voltage = 1.1V p-p
• SNR at 2.56GSPS encode 59.7dBFS at 1.8GHz AIN at -2dBFS and full-scale voltage = 1.1V p-p
• 0.975V, 1.9V and 2.5V DC supply operation
• 9GHz analogue input full power BW (-3dB) and amplitude detect bits for efficient AGC implementation
• Programmable FIR filters for analogue channel loss equalization
• 2 integrated, wideband digital processors per channel 48bit NCO
• Supports 100MHz SPI writes and 50MHz SPI reads, integer clock with divide by 2 and divide by 4 opt
• On-chip dither
• 196 ball BGA package, operating temperature range from -40°C to 85°C

Notes

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party