LTC6952IUKG#PBF

LTC6952 is a high performance, ultralow jitter, JESD204B/C clock generation and distribution IC. It includes a phase locked loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider. This device's eleven outputs can be configured as upto five JESD204B/C subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply eleven general purpose clock outputs for non-JESD204B/C applications. Each output has its own individually programmable frequency divider and output driver. All outputs can also be synchronized and set to precise phase alignment using individual coarse half-cycle digital delays and fine analogue time delays. It is widely used in application such as high performance data converter clocking, wireless infrastructure, test and measurement etc.

• JESD204B/C, subclass 1 SYSREF signal generation
• Low noise integer-N PLL
• EZSync™, ParallelSync™ multichip synchronization
• Flexible outputs can serve as either a device clock or SYSREF signal
• LTC6952Wizard™ software design tool support
• Normalized in-band phase noise floor is -229dBc/Hz typical at (ICP = 11.2mA, TA = 25°C)
• Normalized in-band 1/f phase noise is –281dBc/Hz typical at (CP = 11.2mA, TA = 25°C)
• Output frequency range is 0MHz to 4500MHz
• Operating temperature is -40°C to 125°C
• Package style is 52-lead plastic QFN

Notes

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