CY7C1011DV33-10ZSXIT

CY7C1011DV33-10ZSXIT is a high-performance CMOS static RAM organized as 128K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (active-low CE) and Write Enable (active-low WE) inputs LOW. If Byte Low Enable (active-low BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (active-low BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (active-low CE) and Output Enable (active-low OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (active-low BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15.

• Data retention at 2.0V, automatic power-down when deselected
• Independent control of upper and lower bits
• Easy memory expansion with active-low CE and active-low OE features
• 2Mbit density, 16bits data width, 90nm process technology, 3V to 3.6V voltage range
• 10ns speed, input leakage current is +1µA maximum at (GND < VI < VCC)
• Output leakage current is +1µA maximum at (GND < VOUT < VCC, output disabled)
• VCC operating supply current is 90mA typical at (VCC = Max, f = fMAX = 1/tRC, 100MHz)
• Input capacitance is 8pF maximum at (TA = 25°C, f = 1MHz, VCC = 3.3V)
• Pin-and function-compatible with CY7C1011CV33
• Industrial ambient temperature range from -40°C to +85°C, 44-pin TSOP package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.