MT40A256M16LY-062E:F

MT40A256M16LY-062E:F DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• VDD = VDDQ = 1.2V ±60mV, VPP = 2.5V, -125mV/+250mV, 1.2V pseudo open-drain I/O
• On-die, internal, adjustable VREFDQ generation, sPPR and hPPR capability, JEDEC JESD-79-4 compliant
• 16 internal banks (x4, x8): 4 groups of 4 banks each, 8n-bit prefetch architecture
• 8 internal banks (x16): 2 groups of 4 banks each, command/address (CA) parity
• Programmable data strobe preambles, data strobe preamble training
• Command/address latency (CAL), multipurpose register READ and WRITE capability
• Write levelling, self-refresh mode, low-power auto self refresh, temperature controlled refresh
• Fine granularity refresh, self-refresh abort, maximum power saving, output driver calibration
• Nominal, park, and dynamic on-die termination (ODT), data bus inversion (DBI) for data bus
• 96-ball FBGA package, commercial operating temperature range from 0° ≤ TC ≤ 95°C