MT60B2G8RZ-64B:D

MT60B2G8RZ-64B:D is a DDR5 SDRAM.

• VDD = VDDQ = 1.1V (NOM), VPP= 1.8V (NOM), 1.1V pseudo open-drain I/O
• On-die, internal, adjustable VREF generation for DQ, CA, CS
• 16n-bit prefetch architecture, 1 cycle/2 cycle command structure
• 2N mode, all bank and same bank refresh, multi-purpose command (MPC)
• CS/CA training mode, on-die ECC (bounded fault), ECC transparency and error scrub
• Command-based non-target (NT) nominal, DQ/DQS park, and dynamic WR on-die termination (ODT)
• sPPR and hPPR capability, MBIST/mPPR capability, per-DRAM addressability
• JEDEC JESD-79.5 compliant
• 2 Gig x 8 configuration, 0.312ns at CL = 52 cycle time
• 78-ball FBGA package, -40°C to 0°C commercial temperature range