需要更多?
数量 | 价钱 (含税) |
---|---|
1+ | CNY96.250 (CNY108.7625) |
10+ | CNY96.040 (CNY108.5252) |
25+ | CNY95.810 (CNY108.2653) |
50+ | CNY95.600 (CNY108.028) |
100+ | CNY95.370 (CNY107.7681) |
产品信息
产品概述
SN65LVDM1676DGG is a 16-channel LVDM transceiver. This (integrated termination) consists of sixteen differential line transmitters or receivers (transceiver) that use low-voltage differential signalling (LVDS) to achieve signalling rates up to 200Mbps per transceiver configured as a receiver and up to 650Mbps per transceiver configured as a transmitter. This product is similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247mV into a 50-load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of 100mV with up to 1V of ground potential difference between a transmitter and receiver.
- Bus-terminal ESD protection exceeds 12kV
- Low-voltage TTL (LVTTL) logic input levels are 5V tolerant
- Supply current is 140mA typ at (driver enabled, receiver disabled, RL = 100 ohm)
- Short-circuit output current is 10mA max at (VOD = 0V)
- Power-off output current is 10µA max at (VCC = 1.5V, VO = 2.4V)
- Input capacitance is 5pF typ at (VI = 0.4 sin (4E6πt) + 0.5V)
- 2.5ns typ propagation delay time, low-to-high-level output at (RL = 100 ohm, CL = 10pF)
- 0.1ns typ pulse skew at (RL = 100 ohm, CL = 10pF)
- Operating temperature range from -40°C to 85°C
- 64-pin TSSOP package
技术规格
差分线路收发器
85°C
3.6V
64引脚
LVTTL, M-LVDS
-
-40°C
3V
TSSOP
LVTTL, M-LVDS
16bit
-
法律与环境
进行最后一道重要生产流程所在的地区原产地:Malaysia
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书