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数量 | 价钱 (含税) |
---|---|
1+ | CNY12.490 (CNY14.1137) |
10+ | CNY12.470 (CNY14.0911) |
25+ | CNY12.450 (CNY14.0685) |
50+ | CNY12.430 (CNY14.0459) |
100+ | CNY12.410 (CNY14.0233) |
250+ | CNY12.390 (CNY14.0007) |
500+ | CNY12.370 (CNY13.9781) |
1000+ | CNY12.350 (CNY13.9555) |
产品信息
产品概述
The SN74LS109AN is a dual positive-edge-triggered J-K\ Flip-flop with clear and preset. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. This flip-flop can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
- TTL Input and output
技术规格
74LS109
13ns
8mA
DIP
上升沿
4.75V
74LS
0°C
-
JK
25MHz
DIP
16引脚
互补
5.25V
74109
70°C
-
法律与环境
进行最后一道重要生产流程所在的地区原产地:Malaysia
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书