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数量 | 价钱 (含税) |
---|---|
1+ | CNY6.700 (CNY7.571) |
10+ | CNY6.670 (CNY7.5371) |
50+ | CNY6.630 (CNY7.4919) |
100+ | CNY6.600 (CNY7.458) |
250+ | CNY6.570 (CNY7.4241) |
500+ | CNY6.540 (CNY7.3902) |
1000+ | CNY6.510 (CNY7.3563) |
2500+ | CNY6.470 (CNY7.3111) |
产品信息
产品概述
The SN74LS165AN is a 8-bit parallel-load serial-out Shift Register that shifts the data in the direction of QA toward QH when clocked. parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD\) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with SH/LD\ high enables the other clock input. clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD\ is high. Data at the parallel inputs are loaded directly into the register.
- Complementary outputs
- Direct overriding load (data) inputs
- Gated clock inputs
- Parallel-to-serial data conversion
技术规格
74LS165
1元件
DIP
16引脚
5.25V
74LS
0°C
-
并行至串行、串行至串行
8bit
DIP
4.75V
差分
74165
70°C
-
法律与环境
进行最后一道重要生产流程所在的地区原产地:Malaysia
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书