AS4C128M32MD2A-18BIN

AS4C128M32MD2A-18BIN is a 4Gb (128M x 32) /RZ3RZHUDDR2 SDRAM. The 4Gb mobile low-power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic random-access memory containing 4,294,967,296bits. It is internally configured as an eight-bank DRAM. Each of the x32’s 4,294,967,296bit banks is organized as 16,384 rows by 1024 columns by 32bits. The device uses a double data rate architecture on the command/address (CA) bus to reduce the number of input pins in the system. This device uses a double data rate architecture on the DQ pins to achieve high-speed operation. The double data rate architecture is essentially a 4n pre-fetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or WRITE access for the LPDDR2 effectively consists of a single 4n-bit-wide, one-clock cycle data transfer at the internal SDRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

• VDD2 = 1.14 to 1.30V, VDDCA/VDDQ = 1.14 to 1.30V, VDD1 = 1.70 to 1.95V
• Interface : HSUL-12, data width : x32, clock frequency range : maximum 533MHz
• Four-bit pre-fetch DDR architecture, eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of data(DQS/DQS#)
• DM masks write date at the both rising and falling edge of the data strobe
• Programmable READ and WRITE latencies (RL/WL), auto refresh and self refresh supported
• Low voltage power supply, auto TCSR (temperature compensated self refresh)
• 128M x 32 org, 533MHz maximum clock
• 134-ball FBGA package, industrial temperature range from -40°C to 85°C