CY2305CSXI-1

CY2305CSXI-1 is a low-cost 3.3V zero delay buffer designed to distribute high speed clocks. The CY2305C is an 8-pin version of the CY2309C. It accepts one reference input and drives out five low-skew clocks. It has on-chip phase locked loops (PLLs) which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309C has two banks of four outputs each that are controlled by the select inputs. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the outputs by the select inputs for chip and system testing purposes.

• Standard drive output
• 5-output zero delay buffer
• Zero input and output propagation delay
• Multiple low skew outputs: one input drives five outputs (CY2305)
• 60ps typical cycle-to-cycle jitter (15pF, 66MHz)
• 10 to 100MHz output frequency at 30pF load
• Available in 8 pin SOIC package