S25FL127SABMFI103

S25FL127SABMFI103 is a 128Mb (16MB), 3.0V SPI flash memory. This device connects to a host system via an SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two-bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. The Eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erasing than prior generation SPI programs or erase algorithms. Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at higher clock rates supported, with QIO command, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically.

• 65nm technology node, MirrorBit Eclipse architecture, 128Mb density
• 2.7V to 3.6V supply voltage, 6MBps (50MHz) normal read speed (SDR)
• 13.5MBps (108MHz) fast read speed (SDR), 27MBps (108MHz) dural read speed (SDR)
• 54MBps (108MHz) quad read speed (SDR), 256B / 512B program buffer size
• Common Flash Interface (CFI) data for configuration information
• CMOS 3.0V core, quad-input page programming (QPP) for slow clock systems
• 100,000 program-erase cycles per sector, minimum
• 20 year data retention, minimum
• One time program (OTP) array of 1024 bytes
• Industrial temperature range from -40°C to + 85°C, 16-pin SO package