S25FL128LAGMFA010

S25FL128LAGMFA010 is a flash non-volatile memory using floating gate technology, 65-nm process lithography. The FL-L family connects to a host system via a serial peripheral interface (SPI). In addition, there are double data rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a page programming buffer that allows up to 256bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using FL-L family device at the higher clock rates supported, with quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically.

• 128Mb density, 65-nm floating gate process technology, 133MHz speed
• 8 pin SOIC package
• Temperature range from -40 to +85°C (automotive, AEC-Q100 grade 3)
• Clock polarity and phase modes 0 and 3, modes burst wrap, continuous (XIP), QPI
• Commands normal, fast, dual I/O, quad I/O, dualO, quadO, DDR quad I/O
• Serial flash discoverable parameters (SFDP) for configuration information
• 256bytes page programming buffer, 256Mb (32MB)/128Mb (16MB), 3.0V FL-L flash memory
• Program suspend and resume, erase architecture, uniform 4KB sector erase
• Uniform 32KB half block erase, uniform 64KB block erase, chip erase
• 100000 program/erase cycles, minimum, 20 year data retention, minimum