S26KS512SDPBHI020

S26KS512SDPBHI020 is a Hyper Flash™ memory. It features a hyper bus low signal count DDR interface, that achieves high-speed read throughput. The DDR protocol transfers two data bytes per clock cycle on the data (DQ) signals. A read or write access for the Hyper Flash consists of a series of 16bit wide, one-clock cycle data transfers at the internal Hyper Flash core and two corresponding 8bit wide, one-half-clock-cycle data transfers on the DQ signals. Both data and command/address information are transferred in DDR fashion over the 8bit data bus. The clock input signals are used for signal capture by the Hyper Flash device when receiving command/address/data information on the DQ signals. The read data strobe (RWDS) is an output from the Hyper Flash device that indicates when data is being transferred from the memory to the host. RWDS is referenced to the rising and falling edges of CK during the data transfer portion of read operations.

• Cypress memory 1.8Volt-only, hyper flash memory, 512Mb density
• 65nm MirrorBit process technology, 166MHz speed
• Hyper Flash™ memories use RWDS only as a read data strobe
• Up to 333MBps sustained read throughput, DDR – two data transfers per clock
• 96ns initial random read access time, sequential burst transactions
• INT# output to generate an external interrupt, busy to ready transition, ECC detection
• Separate 1024-byte one-time program array
• 100,000 program/erase cycles, 20 year data retention
• Stand by current is 25 µA typical, sector erase current is 60mA typical
• Industrial temperature range from -40°C to + 85°C, 8-contact WSON package