S27KL0642DPBHI020

S27KL0642DPBHI020 64Mb HYPERRAM™ device is a high-speed CMOS, self-refresh DRAM, with HYPERBUS™ interface. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ interface host. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM (PSRAM). Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The host must confine the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh operation is needed.

• 1.8V / 3.0V interface support, single-ended clock (CK) - 11 bus signals, chip select (CS#)
• 8-bit data bus (DQ[7:0]), hardware reset (RESET#), bidirectional read-write data strobe (RWDS)
• Output at the start of all transactions to indicate refresh latency
• Input during write transactions as write data mask, 200MHz maximum clock rate
• During read transactions RWDS is offset by a second clock, phase shifted from CK
• The phase shifted clock is used to move the RWDS transition edge within the read data eye
• DDR - transfers data on both edges of the clock, data throughput up to 400MBps (3200Mbps)
• 24-ball FBGA package
• Industrial temperature range from (-40°C to 85°C)