需要更多?
数量 | 价钱 (含税) |
---|---|
1+ | CNY38.240 (CNY43.2112) |
10+ | CNY33.860 (CNY38.2618) |
25+ | CNY33.430 (CNY37.7759) |
50+ | CNY33.220 (CNY37.5386) |
100+ | CNY26.260 (CNY29.6738) |
250+ | CNY26.190 (CNY29.5947) |
500+ | CNY26.180 (CNY29.5834) |
产品信息
产品概述
MT48LC8M16A2P-6A:L is a SDR SDRAM. The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks are organized as 4096 rows by 2048 columns by 4bits. Each of the x8’s 33,554,432-bit banks are organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks are organized as 4096 rows by 512 columns by 16 bits. The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.
- Fully synchronous; all signals registered on positive edge of system clock
- Internal, pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Auto precharge, includes concurrent auto precharge and auto refresh modes
- LVTTL-compatible inputs and outputs
- Single 3.3V ±0.3V power supply
- Timing – cycle time : 6ns at CL = 3 (x16 only)
- 8 Meg x 16 architecture
- 54-pin TSOP II (400 mil) package
- Commercial operating temperature range from 0°C to 70°C
警告
该产品的市场需求较大, 导致交货时间延长。交货日期可能会有延迟。该产品不在折扣范围内。
技术规格
SDR
8M x 16位
TSOP-II
3.3V
0°C
-
No SVHC (17-Dec-2015)
128Mbit
167MHz
54引脚
表面安装
70°C
MSL 3 - 168小时
技术文档 (1)
法律与环境
进行最后一道重要生产流程所在的地区原产地:Singapore
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书