74HC166D-Q100J

74HC166D-Q100J is a 8bit parallel-in/serial out shift register. This device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (active-low PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When active-low PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (active-low CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the automotive electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

• Wide supply voltage range from 2.0V to 6.0V
• CMOS low power dissipation, high noise immunity
• Latch-up performance exceeds 100mA per JESD 78 Class II Level B
• Synchronous parallel-to-serial applications, synchronous serial input for easy expansion
• CMOS input level, complies with JEDEC standards, ESD protection
• Input leakage current is ±0.1μA max at (VI=VCC or GND;VCC = 4.5V, 25°C)
• Supply current is 8μA max at (VI=VCC or GND;IO = 0A;VCC = 6V, 25°C)
• Input capacitance is 3.5pF typical at (25°C)
• Propagation delay is 50ns typical at (VCC = 2V, 25°C)
• Operating temperature range from -40°C to +125°C, SO16 package

警告

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.