74HC4040PW,118

74HC4040PW,118 is a 12-stage binary ripple counter with a clock input (active-low CP), an overriding asynchronous MR input and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of active-low CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of active-low CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. It features ESD protection (HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V). It complies with JEDEC standards (JESD8C (2.7V to 3.6V), JESD7A (2.0V to 6.0V). It is used in applications such as frequency dividing circuits, time delay circuits, control counters.

• Wide supply voltage range from 2.0V to 6.0V
• CMOS low power dissipation, high noise immunity
• CMOS input level, input leakage current is ±0.1μA max at (25°C)
• Supply current is 8.0μA maximum at (VI = VCC or GND; IO = 0A; VCC = 6V, 25°C)
• Input capacitance is 3.5pF typical at (25°C)
• Propagation delay is 47ns typical at (VCC = 2.0V, 25°C)
• Transition time is 19ns typical at (VCC = 2.0V, 25°C)
• Pulse width is 14ns typical at (VCC = 2.0V, 25°C)
• Operating temperature range from -40°C to +125°C
• TSSOP16 package

警告

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