74LVC1G332GW,125

74LVC1G332GW,125 is a single 3-input OR gate. This device inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It complies with JEDEC standard (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 5.5V
• High noise immunity, overvoltage tolerant inputs to 5.5V
• CMOS low power dissipation, direct interface with TTL levels
• OFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 250mA
• Input leakage current is ±0.1μA typ at (VCC = 0V to 5.5V;VI = 5.5V or GND, -40°C to +85°C)
• Supply current is 0.1μA typ at (VCC = 1.65V to 5.5V;VI = VCC or GND;IO = 0A, -40°C to +85°C)
• Input capacitance is 3pF typical at (VCC = 3.3V;VI = GND to VCC, -40°C to +85°C)
• Propagation delay is 4.7ns typical at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C, TSSOP6 package

警告

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.