MPC565CZP56

The MPC565CZP56 is a 32-bit Microcontroller a member of the MPC500 family of microprocessors that implements the power architecture instruction standard architecture. The MPC565 is integrated with a floating point unit, an advanced peripheral set and 1MB of flash memory on a single chip. The device incorporates 36kB internal RAM, 40-channel 10-bit A/D converter, Three TouCAN modules (TouCAN A, TouCAN B, TouCAN C) and 56 general-purpose I/O pins.

• An MPC500 core with a floating point unit (FPU) and a burst buffer controller (BBC)
• Unified system integration unit (USIU)
• Flexible memory controller
• Enhanced interrupt controller
• 3 Time processor units (TPU3)
• 22 Timer channel modular I/O system (MIOS14)
• 2 Enhanced queued analog to digital converters (QADC64E A, QADC64E B)
• 2 Queued serial multi-channel modules (QSMCM A, QSMCM B)
• Queued serial peripheral interface (QSPI)
• 2 Serial controller interfaces (SCI/UART)
• J1850 (DLCMD2) communications module
• Nexus debug port (class 3) - IEEE-ISTO 5001-1999
• JTAG and background debug mode (BDM)
• 40MHz Operation (56MHz operation is optional)