AM3352BZCZ100

The Sitara AM335x series Sitara™ Microprocessor based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI. The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ graphics accelerator subsystem provides 3D graphics acceleration to support display and gaming effects. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos and others.

• Up to 1GHz Sitara™ ARM® Cortex® -A8 32-Bit RISC processor
• 64kB General-purpose on-chip memory controller (OCMC) RAM
• External memory interfaces (EMIF)- General-purpose memory controller (GPMC)
• Error locator module (ELM)
• Programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS)
• Five ADPLLs to generate system clocks
• Two non-switchable power domains (Real-time clock (RTC), wake-up logic (wake-up))
• Real-time date (day-month-year-day of week) and time (hours-minutes-seconds) information
• Up to two USB 2.0 high-speed OTG ports with integrated PHY
• Up to two controller-area network (CAN) ports
• Programmable high-quality image anti-aliasing
• Fully virtualized memory addressing for OS operation in an unified memory architecture
• LCD controller
• 12-bit successive approximation register (SAR) ADC
• Up to Three enhanced high-resolution PWM modules (eHRPWMs)
• Two programmable real-time units (PRUs)
• 12kB Shared RAM with single-error detection (parity)
• Peripherals inside the PRU-ICSS
• Power, reset and clock management (PRCM) module
• Device identification
• Debug interface support
• Inter-processor communication (IPC)
• Security - Crypto hardware accelerators (AES, SHA, RNG) and secure boot