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数量 | 价钱 (含税) |
---|---|
1+ | CNY6.260 (CNY7.0738) |
10+ | CNY5.970 (CNY6.7461) |
50+ | CNY5.690 (CNY6.4297) |
100+ | CNY5.400 (CNY6.102) |
250+ | CNY5.120 (CNY5.7856) |
500+ | CNY4.830 (CNY5.4579) |
1000+ | CNY4.540 (CNY5.1302) |
2500+ | CNY4.250 (CNY4.8025) |
产品信息
产品概述
The SN74LVC1G125DBVT is a single Bus Buffer Gate with 3-state outputs. The output is disabled when the output-enable (OE) input is high. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. The device contains one buffer gate device with output enable control and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.
- Provides down translation to VCC
- IOFF Supports live insertion, partial-power-down mode and back-drive protection
- Latch-up performance exceeds 100mA per JESD 78, class II
- Inputs accept voltages to 5.5V
- 3.7ns at 3.3V Propagation delay (tpd)
- 10µA ICC Low power consumption
- ±24mA Output drive at 3.3V
- Green product and no Sb/Br
技术规格
缓冲、非反相
SOT-23
5引脚
5.5V
741G125
125°C
-
74LVC1G125
SOT-23
1.65V
74LVC
-40°C
-
技术文档 (1)
SN74LVC1G125DBVT 的替代之选
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法律与环境
进行最后一道重要生产流程所在的地区原产地:China
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书