SN74LVC2G74DCUR

The SN74LVC2G74DCUR is a single Positive-edge-triggered D-type Flip-flop with clear and preset. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D-input can be changed without affecting the levels at the outputs.

• 5.9ns at 3.3V Maximum TPD
• Low power consumption
• IOFF supports live insertion, partial-power-down mode and back-drive protection
• Latch-up performance exceeds 100mA per JESD 78
• ESD protection exceeds JESD 22

警告

该设备静电防护措施有限, 存放时引线应短接在一起, 或将设备放置在导电泡漠中, 以防止静电对MOS门造成损坏.