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数量 | 价钱 (含税) |
---|---|
1+ | CNY76.240 (CNY86.1512) |
10+ | CNY55.410 (CNY62.6133) |
25+ | CNY53.000 (CNY59.890) |
50+ | CNY50.590 (CNY57.1667) |
100+ | CNY48.170 (CNY54.4321) |
250+ | CNY47.210 (CNY53.3473) |
500+ | CNY46.250 (CNY52.2625) |
产品信息
产品概述
The MC100EPT21DTG is a 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator ideal for applications which requires the translation of a clock or data signal. Because LVPECL (positive ECL), LVDS and positive CML input levels and LVTTL/LVCMOS output levels are used, only 3.3V and ground are required. The VBB output allows this EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, VBB output is tied to the D input and D is driven for a non-inverting buffer or VBB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01F capacitor. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single-ended direct connection or port to another device.
- LVPECL/LVDS/CML Inputs
- LVTTL/LVCMOS Outputs
- 24mA TTL outputs
- Contains temperature compensation
- <gt/>275MHz Typical maximum frequency
技术规格
2Inputs
1.4ns
TSSOP
3V
-40°C
电平转换器
-
No SVHC (27-Jun-2024)
24mA
8引脚
TSSOP
3.6V
85°C
-
MSL 3 - 168小时
技术文档 (1)
法律与环境
进行最后一道重要生产流程所在的地区原产地:Malaysia
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书