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数量 | 价钱 (含税) |
---|---|
5+ | CNY5.760 (CNY6.5088) |
10+ | CNY2.960 (CNY3.3448) |
100+ | CNY1.930 (CNY2.1809) |
500+ | CNY1.590 (CNY1.7967) |
1000+ | CNY1.240 (CNY1.4012) |
5000+ | CNY1.150 (CNY1.2995) |
10000+ | CNY1.060 (CNY1.1978) |
产品信息
产品概述
The SN74LV165APWR is a 8-bit parallel-load Shift Register designed for 2 to 5.5V VCC operation. When it is clocked, data is shifted toward the serial output QH. parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. It features a clock-inhibit function and a complemented serial output, QH. clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are enabled while SH/LD\ is held low, independently of the levels of CLK, CLK INH or SER.
- Support mixed-mode voltage operation on all ports
- Ioff Supports partial-power-down mode operation
- Latch-up performance exceeds 250mA per JESD 17
- Green product and no Sb/Br
技术规格
74LV165
1元件
TSSOP
16引脚
5.5V
74LV
-40°C
-
并行至串行
8bit
TSSOP
2V
差分
74165
85°C
-
技术文档 (1)
法律与环境
进行最后一道重要生产流程所在的地区原产地:China
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书