74LVC1G32GV,125

74LVC1G32GV,125 is a single 2-input OR gate. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

• Wide supply voltage range from 1.65V to 5.5V
• Overvoltage tolerant inputs to 5.5V, high noise immunity
• CMOS low power dissipation, ±24mA output drive (VCC = 3.0V)
• IOFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 250mA, direct interface with TTL levels
• Input transition rise and fall rate is 20ns/V max at VCC = 1.65V to 2.7V
• Propagation delay is 10.5ns max at -40°C to +125°C, VCC = 1.65V to 1.95V
• Total power dissipation is 250mW maximum at Tamb = -40°C to +125°C
• SC-74A package
• Temperature range from -40°C to +125°C

注释

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