AS4C32M16SC-7TIN

AS4C32M16SC-7TIN is a four-bank synchronous DRAM organized as 4 banks x 8Mbit x 16. This synchronous device achieves high-speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input, and output circuits are synchronized with the positive edge externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device.

• Fully synchronous to positive clock edge, fast clock rate: 133MHz
• Multiple burst read with single write operation
• Four banks controlled by BA0 and BA1, data mask for byte control (x16,x32)
• Programmable mode registers, CAS latency: 1 or 2 or 3, burst Length: 1, 2, 4, 8 or full page
• Automatic and controlled precharge command, LVTTL interface
• Auto refresh and self-refresh, 8192 refresh cycles/64ms (7.8µs) T≦85°C
• Power down mode, data mask for read/write control (x8, x16, x32)
• Random column address every CLK (1-N rule), single +3.3V±0.3V power supply
• 54 pin TSOP II package
• Industrial temperature range from -40°C to 85°C