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数量 | 价钱 (含税) |
---|---|
1+ | CNY174.660 (CNY197.3658) |
10+ | CNY125.540 (CNY141.8602) |
25+ | CNY118.240 (CNY133.6112) |
100+ | CNY114.590 (CNY129.4867) |
250+ | CNY110.940 (CNY125.3622) |
500+ | CNY107.290 (CNY121.2377) |
产品信息
产品概述
AD9525 is a low jitter clock generator with eight LVPECL outputs. It is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. It provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO. The VCO input and eight LVPECL outputs can operate upto a frequency of 3.6GHz. All outputs share a common divider that can provide a division of 1 to 6. It offers a dedicated output that can be used to provide a programmable signal for resetting or synchronizing a data converter. The output signal is activated by a SPI write. It is used in applications such as LTE and multicarrier GSM base stations, clocking high speed ADCs, DACs, ATE and high performance instrumentation, 40/100Gb/sec OTN line side clocking, cable/DOCSIS CMTS clocking, test and measurement.
- Integrated ultralow noise synthesizer
- 8 differential 3.6GHz LVPECL outputs and 1 LVPECL SYNC output or 2 CMOS SYNC outputs
- 2 differential reference inputs and 1 single-ended reference input
- Input sensitivity is 200mV p-p typical at (frequency at 122.88MHz)
- Input frequency range from 0MHz to 500MHz
- Rise time/fall time (20% to 80%) is 105ps typical
- Operating temperature range from -40°C to +85°C
- Package style is 48-lead lead frame chip scale (LFCSP-WQ)
注释
ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party
技术规格
时钟发生器
8输出
3.465V
48引脚
85°C
-
No SVHC (21-Jan-2025)
3.6GHz
3.135V
LFCSP
-40°C
-
MSL 3 - 168小时
法律与环境
进行最后一道重要生产流程所在的地区原产地:Philippines
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书