AD9546BCPZ

AD9546 is a dual DPLL digitized clock synchronizer. It incorporates digitized clocking technology that efficiently transports and distributes clock signals in systems. Digitized clocking allows the design of flexible and scalable clock transport systems with well controlled phase (time) alignment. These characteristics make the AD9546 a leading choice for the design of network equipment that must meet the synchronization requirements for IEEE® 1588™ boundary clocks per ITU-T G.8273.2 Class D. Digitized clocking is also relevant in applications requiring the accurate transport of frequency and phase to multiple usage endpoints. It supports existing and emerging international telecommunications union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks.

• Digitized clock transport subsystem, fast DPLL locking modes
• Cross point mux interconnects reference inputs to PLLs
• Supports embedded (modulated) input/output clock signals
• External EEPROM support for autonomous initialization
• Typical VDDIOx current (IVDDIOx) is 5mA (aggregate current for all VDDIOx pins (where x=AorB)
• Typical power dissipation configuration is 585mW (fOSC=49.152MHz crystal; two active DPLLs)
• Typ input reference On/Off-differential (AC-coupled mode) is 20mW (Ref frequency (fREF)=19.44MHz)
• Typical input reference On/Off (single-ended) is 13mW (fREF=19.44MHz, VDD=1.8V)
• Input frequency range from 20 to 300MHz (VDD=1.8V)
• 48-lead LFCSP package, temperature range from -40°C to +85°C

注释

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party