AD9548BCPZ

AD9548 is a quad/octal input network clock generator/synchronizer provides synchronization for many systems, including synchronous optical networks (SONET/SDH). This generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for the reduction of input time jitter or phase noise associated with the external references. This continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry. Application includes network synchronization, clean-up of reference clock jitter, GPS 1 pulse per second synchronization, SONET/SDH clocks up to OC-192, including FEC, stratum 2 holdover, jitter clean-up, and phase transient control, stratum 3E and Stratum 3 reference clocks., wireless base station controllers, cable infrastructure, data communications.

• Supports Stratum 2 stability in holdover mode
• Supports reference switchover with phase build-out
• Auto/manual holdover and reference switchover
• Reference validation and frequency monitoring (1ppm)
• Programmable input reference switchover priority
• On-chip EEPROM to store multiple power-up profiles
• Software controlled power-down
• Operating temperature rating range from -40 to +85°C
• 88-lead frame chip scale package [LFCSP-VQ]

注释

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party