MAX5864ETM+

The MAX5864ETM+ is an ultra low power, high dynamic performance, 22Msps analogue front end in 48 pin TQFN package. This highly integrated analogue front end integrates dual 8bit receive ADCs and dual 10bit transmit DACs while providing highest dynamic performance at ultra low power. The ADCs’ analogue I-Q input amplifiers are fully differential and accept 1VP-P full scale signals. Typical I-Q channel phase matching is ±0.1° and amplitude matching is ±0.03dB. The ADCs has 48.5dB SINAD and 69dBc spurious free dynamic range (SFDR) at fIN = 5.5MHz and fCLK = 22Msps. The DACs’ analogue I-Q outputs are fully differential with ±400mV full scale output and 1.4V common mode level. Typical I-Q channel phase match is ±0.15° and amplitude match is ±0.05dB. The DACs also has dual 10bit resolution with 71.7dBc SFDR and 57dB SNR at fOUT = 2.2MHz and fCLK = 22MHz. The ADCs and DACs operate simultaneously or independently for frequency division duplex (FDD) and time division duplex (TDD) modes.

• Analogue supply voltage range from 2.7V to 3.3V
• Operating temperature range from -40°C to 85°C
• Internal 1.024V voltage reference/external reference
• 3-wire serial interface controls power-down and transceiver modes of operation
• Ultra low power, 42mW at fCLK = 22MHz (transceiver mode), 34mW at fCLK=15.36MHz (transceiver mode)
• Excellent gain/phase match (±0.1° phase, ±0.03dB gain at fIN = 5.5MHz (ADC))
• 1.8V to 3.3V digital output level (TTL/CMOS compatible)
• Multiplexed parallel digital input/output for ADCs/DACs
• Integral nonlinearity of ±0.15LSB and differential nonlinearity of ±0.15LSB (ADC)
• ±0.24%FS offset error of ADC and ±0.77 %FS gain error of ADC

警告

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.

注释

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