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数量 | 价钱 (含税) |
---|---|
1+ | CNY142.170 (CNY160.6521) |
10+ | CNY131.790 (CNY148.9227) |
25+ | CNY127.610 (CNY144.1993) |
50+ | CNY124.480 (CNY140.6624) |
100+ | CNY119.100 (CNY134.583) |
产品概述
IS43QR16512A-083TBLI 512Mx16 8Gbit DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with eight-banks (2 bank groups each with 4 banks for x16, and 4 bank groups each with 4 banks for x8). The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Operation begins with the registration of an ACTIVATE command, which is then followed by a read or write command.
- Standard voltage is VDD = VDDQ = 1.2V, VPP=2.5V
- High-speed data transfer rates with system frequency up to 2933Mbps
- Data Integrity, auto self refresh (ASR) by DRAM built-in TS, auto refresh and self refresh modes
- DRAM access bandwidth, separated IO gating structures by bank groups, self refresh abort
- Signal synchronization, write levelling via MR settings, read levelling via MPR
- Reliability and error handling, command/address parity, data bus write CRC
- Signal integrity, internal VREFDQ training, read preamble training, gear down mode
- Power saving and efficiency, POD with VDDQ termination, command/address latency (CAL)
- 96-ball FBGA package
- Industrial temperature rating range from -40°C to +95°C
技术规格
DDR4
512M x 16位
FBGA
1.2V
-40°C
-
8Gbit
1.2GHz
96引脚
表面安装
95°C
No SVHC (16-Jul-2019)
技术文档 (1)
法律与环境
进行最后一道重要生产流程所在的地区原产地:Taiwan
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书