MT47H128M16RT-25E IT:C

MT47H128M16RT-25E IT:C is a DDR2 SDRAM. The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single READ or WRITE operation for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, two-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. The DDR2 SDRAM provides programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

• VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
• JEDEC-standard 1.8V I/O (SSTL-18-compatible)
• DLL to align DQ and DQS transitions with CK, 8 internal banks for concurrent operation
• Programmable CAS latency (CL), posted CAS additive latency (AL)
• Adjustable data-output drive strength, 64ms, 8192-cycle refresh
• On-die termination (ODT), supports JEDEC clock jitter specification
• 128 Meg x 16 configuration
• Timing – cycle time : 2.5ns at CL = 5 (DDR2-800)
• 84-ball BGA package
• Industrial operating temperature range from (-40°C ≤ TC ≤ +95°C)