需要更多?
数量 | 价钱 (含税) |
---|---|
1+ | CNY32.280 (CNY36.4764) |
10+ | CNY30.080 (CNY33.9904) |
25+ | CNY28.650 (CNY32.3745) |
50+ | CNY28.500 (CNY32.205) |
100+ | CNY27.740 (CNY31.3462) |
250+ | CNY26.930 (CNY30.4309) |
500+ | CNY26.260 (CNY29.6738) |
产品信息
产品概述
MT48LC16M16A2P-6A:G is a SDR SDRAM. The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks are organized as 8192 rows by 2048 columns by 4bits. Each of the x8’s 67,108,864-bit banks are organized as 8192 rows by 1024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks are organized as 8192 rows by 512 columns by 16 bits. The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
- Fully synchronous; all signals registered on positive edge of system clock
- Internal, pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Auto precharge, includes concurrent auto precharge and auto refresh modes
- LVTTL-compatible inputs and outputs
- Single 3.3V ±0.3V power supply
- 167MHz clock frequency, timing – cycle time: 6ns at CL = 3 (x8, x16 only)
- 16 Meg x 16 architecture
- 54-pin TSOP II package
- Commercial operating temperature range from 0°C to +70°C
警告
该产品的市场需求较大, 导致交货时间延长。交货日期可能会有延迟。该产品不在折扣范围内。
技术规格
SDR
16M x 16位
TSOP-II
3.3V
0°C
-
No SVHC (17-Dec-2015)
256Mbit
167MHz
54引脚
表面安装
70°C
MSL 3 - 168小时
技术文档 (1)
法律与环境
进行最后一道重要生产流程所在的地区原产地:Singapore
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书