74LV74PW-Q100J

74LV74PW-Q100J is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (n active-low SD) and reset (n active-low RD) inputs, and complementary nQ and n active-low Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. This product has been qualified to the automotive electronics council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. It features ESD protection (MIL-STD-833, method 3015 exceeds 2000V, HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V (C = 200pF, R = 0 ohm).

• Wide supply voltage range from 1V to 5.5V
• Optimized for low voltage applications from 1V to 3.6V
• CMOS low power dissipation, direct interface with TTL levels (2.7V to 3.6V)
• Latch-up performance exceeds 100mA per JESD 78 Class II Level B
• Input leakage current is ±1μA maximum at (VI=VCC or GND;VCC = 5.5V, -40°C to +85°C)
• Supply current is 20μA maximum at (VI= VCC or GND;IO = 0A;VCC = 5.5V, -40°C to +85°C)
• Input capacitance is 3.5pF typical at (-40°C to +85°C)
• Propagation delay is 70ns typical at (VCC = 1.2V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSSOP14 package

警告

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.