74LVC1G00GV,125

The 74LVC1G00GV is a single 2-input NAND Gate with input can be driven from either 3.3V or 5V devices. This feature allows the use of these devices in a mixed 3.3V and 5V environment. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

• High noise immunity
• Complies with JEDEC standard - JESD8-7, JESD8-5 and JESD8-B/JESD36
• ±24mA Output drive (VCC = 3V)
• CMOS low power consumption
• Latch-up performance exceeds 250mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5V
• ESD protection - HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V

注释

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.