74LVC1G32GW-Q100H

74LVC1G32GW-Q100H is a single 2-input OR gate. This device inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the automotive electronics council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 5.5V
• High noise immunity, CMOS low power dissipation
• IOFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 250mA, direct interface with TTL levels
• Complies with JEDEC standard, overvoltage tolerant inputs to 5.5V
• Input leakage current is ±0.1μA typ at (VI= 5.5V or GND;VCC = 0V to 5.5V,-40°C to +85°C)
• Supply current is 0.1μA typ at (VI= 5.5V or GND;IO = 0A;VCC = 1.65V to 5.5V, -40°C to +85°C)
• Input capacitance is 5pF typ at (VCC = 3.3V;VI= GND to VCC, -40°C to +85°C)
• Propagation delay is 3.1ns typ at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C, TSSOP5 package

警告

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.