74LVC3G07GT,115

74LVC3G07GT,115 is a triple buffer with open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. It complies with JEDEC standard (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8-B/JESD36 (2.7V to 3.6V).It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 5.5V
• 5V tolerant input/output for interfacing with 5V logic
• High noise immunity, CMOS low power consumption
• Latch-up performance exceeds 250mA, direct interface with TTL levels
• Inputs accept voltages upto 5V, input leakage current is ±0.1μA typical
• Supply current is 0.1μA typ at (VI=5.5V or GND;IO = 0A;VCC = 1.65V to 5.5V, Tamb = -40°C to +85°C)
• Input capacitance is 2.5pF typ at (Tamb = -40°C to +85°C)
• Propagation delay is 2.9ns typ at (VCC = 1.65V to 1.95V, Tamb = -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• XSON8 package

警告

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