74AUP2G80DC,125

The 74AUP2G80DC is a dual positive-edge triggered D-type Flip-flop with low-power. Information on the data input is transferred to the Q\ output on the low-to-high transition of the clock pulse. The input pin D must be stable one setup time prior to the low-to-high clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 to 3.6V. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

• High noise immunity
• IOFF Circuitry provides partial power-down mode operation
• Latch-up performance exceeds 100mA per JESD 78, class II
• Low noise overshoot and undershoot <lt/>10% of VCC
• 0.9μA Maximum low static power consumption