74HC107D,652

The 74HC107D is a dual negative edge triggered JK Flip-flop featuring individual J and K inputs, clock (CP\) and reset (R\) inputs and complementary Q and Q\ outputs. The reset is an asynchronous active low input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flop. The J and K inputs must be stable one set-up time prior to the high-to-low clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

• CMOS Input levels
• Complies with JEDEC standard No. 7A

警告

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.