74HC138D-Q100,118

74HC138D-Q100,118 is a 3-to-8 line inverting decoder/demultiplexer. It decodes three binary weighted address inputs to eight mutually exclusive outputs (active-low Y0 to active-low Y7). The device features three enable inputs. Every output will be HIGH unless active-low E1 and active-low E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the automotive electronics council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

• Wide supply voltage range from 2V to 6V
• CMOS low power dissipation, high noise immunity
• Latch-up performance exceeds 100mA per JESD 78 Class II Level B
• Demultiplexing capability, multiple input enable for easy expansion
• Ideal for memory chip select decoding, active LOW mutually exclusive outputs
• CMOS input level, complies with JEDEC standards, ESD protection
• Input leakage current is ±0.1μA max at (VI=VCC or GND; VCC = 6V, Tamb = 25°C)
• Supply current is 8μA max at (VI=VCC or GND;IO = 0A;VCC = 6V, Tamb = 25°C)
• Propagation delay is 41ns typical at (VCC = 2V, Tamb = 25°C)
• Operating temperature range from -40°C to +125°C, SO16 package

警告

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