产品信息
产品概述
The HEF4017BT is a 5-stage Johnson Decade Counter with ten spike-free decoded active high outputs (Q0 to Q9), an active low carry output from the most significant flip-flop (Q5\-9), active high and active low clock inputs (CP0, CP1\) and an overriding asynchronous master reset input (MR). The counter is advanced by either a low-to-high transition at CP0 while CP1\ is low or a high-to-low transition at CP1\ while CP0 is high. When cascading counters, the Q5\-9 output, which is low while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A high on MR resets the counter to zero (Q0 = Q5\-9 = high, Q1 to Q9 = low) independent of the clock inputs (CP0, CP1\). Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times.
- Automatic counter correction
- Tolerant of slow clock rise and fall times
- Fully static operation
- Standardized symmetrical output characteristics
- Complies with JEDEC standard JESD 13-B
技术规格
HEF4017
30MHz
SOIC
16引脚
15V
4017
70°C
MSL 1 -无限制
十进位
5
SOIC
3V
HEF4000
-40°C
-
No SVHC (21-Jan-2025)
HEF4017BT,653 的替代之选
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法律与环境
进行最后一道重要生产流程所在的地区原产地:Netherlands
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书