NPIC6C595PW,118

The NPIC6C595PW is a 8-bit serial-in/serial or parallel-out Shift Register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset input (MR\). A low on MR\ resets both the shift register and storage register. Data is shifted on the low-to-high transitions of the SHCP input. The data in the shift register is transferred to the storage register on a low-to-high transition of the STCP input and to the Q7S output on a low-to-high transition of the SHCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. Data in the storage register drives the gate of the output extended-drain NMOS transistor whenever the OE\ is low. A high on OE\ causes the outputs to assume a high-impedance OFF-state.

• Low power consumption
• All registers cleared with single input
• Eight power EDNMOS transistor outputs of 100mA continuous current
• 250mA Current limit capability
• 33V Output clamping voltage
• 30mJ Avalanche energy capability

警告

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