产品信息
产品概述
The SN74LS373DW is an octal transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. The eight latch of the LS373 ate transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up. Schmitt-trigger buffered inputs at the enable/clock lines of the S373 device simplify system design as AC and DC noise rejection is improved by typically 400mV due to the input hysteresis.
- Full parallel access for loading
- Buffered control inputs
- Clock-enable input has hysteresis to improve noise rejection
- PNP Inputs reduce DC loading on data lines
- Green product and no Sb/Br
技术规格
74LS373
三态
24mA
SOIC
4.75V
8位
74373
70°C
-
D型透明
12ns
SOIC
20引脚
5.25V
74LS
0°C
-
技术文档 (1)
法律与环境
进行最后一道重要生产流程所在的地区原产地:Malaysia
进行最后一道重要生产流程所在的地区
RoHS
RoHS
产品合规证书